Post Graduate Diploma in Embedded  System and VLSI  Design is a six months (24 weeks) full time programme divided into two Embedded and VLSI modules with one major project. The syllabus of the course has been focused to cover practical engineering applications, presenting the theory behind applications and implementation. The programme prepares skilled  Industry professionals (System Analysts, Design  Engineers/ Programmers, IT Consultants) through classroom lectures and practical training, using latest  software tools and  technology.

Course Highlights

· 24 weeks full-time Post-Graduate Course
· Evaluation at the module level followed by an exam at the end of each term
· Intake - 80 seats (maximum)
· Curriculum designed in consultation with industry experts and leading academicians (Technical  Advisory Committee)
·  Well-equipped laboratory
· Well-equipped library with access to International Journals
· Extensive hands on sessions
· Limited Internet access
· Exposure to soft skills
· Placement assistance
· ISO Certified training process
· Resourceful Faculty
· Quality Course Material
· Access to state-of-the-art computing facilities
· Hostel Facilities

Eligibility

B.E / B.Tech., M.E/ M Tech. or equivalent in Electronics/Electrical/ Electrical & Electronics /Computer/Electronics and Telecommunication/ Instrumentation/ M. Sc (Electronics). Students appearing for the final semester examination are also eligible.

Candidates should have minimum 60% in last qualifying degree. Also Candidates should not have less than 60% in more than one of the academic qualifications. Candidate who have less than 50% in any of the qualifications are Not Eligible. Students who have appeared for final semester Examinations are also eligible for this course.

Selection Process & Declaration of Result

·     There would be an Online Exam.

·     Result will be prepared on the basis of marks secured in Online Exam and past academic record.

• List of selected and waitlisted candidates (if any) would be declared from the Result.

• In case, any selected candidate does not pay first installment of fee by specified date, his/her seat will be treated as vacant. Such vacant seats will be allotted to candidates in waiting list

• Seats from waitlist will be filled only against the vacant seats.

• In case any waitlisted candidate fails to do so his/her seat will allocated to the next candidate in waitlisted merit list.

• Waitlisted candidates will contact CDAC, Noida on specified date and time.

• In case there are vacant seats after the dates for submission of fee by merit and waitlisted candidates is over, they will be filled up from the left over of the selected & wait listed candidates up till one week(5 working days inclusive of the commencement date) from the commencement of the course.

• Since result awaited candidates of eligible qualification may also apply for the programme, they have to submit the final year marksheet or completion certificate before they complete their programme from CDAC. Failure of same may lead to withholding of their PG diploma certificate & such candidates shall not be considered for placement assistance through CDAC.

Course Fees

1.        Fee for the Course is Rs. 55,150/- inclusive of service Tax @10.3% payable in two installments (First installment Rs. 33,090/- and Second Rs. 22,060/-) by Demand Draft in favour of CDAC, NOIDA payable at Noida. First installment of fee is to be deposited by the selected/waitlisted candidates on or before the specified date. The second installment is to be paid on the first working day of the programme i.e. commencement date of the programme. In case a student wishes to transfer from one course to another (subject to qualifying the entrance exam for that course), it would be treated as a refund case and policy of refund given below shall be applicable.

 Rules for Refund of Course Fees  

The course fees paid by the candidate shall be refunded as per the below mentioned rules:

1.    The fees shall be refunded only if the candidate applies for the refund or transfer within one week(5 working days) inclusive of the commencement date of the course. Request shall be accepted till
5 PM on the last date.

2.    25% of the course fees shall be deducted, balance fees shall be refunded within 30 days from the commencement of the course. Such cancelled seat will be allotted to the next waitlisted candidate.

3.    Any request for refund of fees shall not be entertained after one week (5 working days) inclusive of the commencement date of the course.  

Syllabus for Entrance Test

The Entrance Exam would be conducted in 2 hrs slots and would be  consisting of Multiple Choice Questions based on the following: 

1. Digital Electronics

2. Computer Architecture

3. Computer Network

4. Introduction to Computer

5. Operating System

6. Introduction of   C Language

7. Programming Concepts (Not related with language, only concepts)

8. Basics of Electronics

9. Introduction to Computers

10. General English (Comprehension, Correct the sentences, Correct the sentences)

11. Logical Reasoning (Series, Analogy Blood relation etc.)

12. Quantitative Aptitude (ratio & proportion, Percentage, Profit & loss, Time and work)

Evaluation Methodology

The evaluation methodology consist of continuous evaluation by means of class tests, seminars and lab assignment evaluations. There would be one module exam at the end of both modules and project evaluation.

 The evaluation of the students is based on the following distribution of the marks:

 Instructions

1.    The student should have total of 75% attendance in theory and practical classes in order to be eligible for Participation Certificate of the course. In case attendance falls below 75% a student may still be awarded Participation Certificate on the basis of genuine grounds and their approval from Executive Director.

2.    The grade criteria for each module is as follows:             

3.    The candidates who would be absent/failed in the module end exams will be given one more chance to re-appear in the exam at the end of the program with the permission of Head of School.  4.    Every eligible candidate would be awarded Participation Certificate and Performance Statement (which would include Grade Sheet and Project Certificate)

Project                                                                                                                                     

Students have to do ONE project which is the part of the PGDEVD course at the end of the module. The project work is thoroughly evaluated. The project work is allotted  50 marks *, the categorization of which is as follows: 

 *  The project is one part of the total marks assessment which is also mentioned  in Evaluation   Methodology Section.  

GUIDELINES FOR PLACEMENT

The objective of the Placement Cell is to provide PLACEMENT ASSISTANCE to all the students registered with C-DAC, Noida for Career Courses for a duration of 6 months and above subject to certain criteria. List of companies who have recruited students from this course are:

 PLACEMENT SCHEDULE (TENTATIVE)                 

COURSE CONTENTS

VLSI Module

DIGITAL DESIGN 

· Introduction of Digital electronics
· Digital signals and basic circuits
· Number system
· Boolean algebra
· Combinational logic design, standard representation for logic functions
· K- map representations and simplification for logic functions
· Combinational logic design using MSI chips
· Mux
· D- Mux
· Decoder
· Encoder
· Adder
· Sub tractor
· Sequential logic design
· 1-bit memory cell
· Application of Flip-flops and their characteristics
· Synchronous ad asynchronous counter
· Clocked sequential circuits
· State machines

HDL Programming

VERILOG

• Introduction and overview of VERILOG
• History and major capabilities
• Development flow and Verilog modules
• Description of different modeling
• Data flow
• Behavior
• Structural design
• Simulation of the design.
• Language element, identifiers, comments, format,
• System task
• Function
• Compiler directives
• Data types: Net, Wire and tri types, wor and trior nets, wand and triand nets, tri register nets, vector and scalar nets, integer, integer register and time register
• Operators: Arithmetic and logical, signed and unsigned operators, conditional operator, shift operator, concatenation operator, bit wise operator and relational operator
• Gate level modeling
• Multiple input output gates
• Tri state gates
• Pull gates
• Array of instance and implicit nets
• Structural statement
• Module instantiation, unconnected ports, external ports and other examples
• Data flow modeling, continuous assignment
• Net declaration assignment
• Delays and net delays
• Behavioral modeling
• Procedural construct
• Initial statement
• Always statement
• Timing control
• Delay control
• Event control
• Sequential statement
• Parallel block statement
• Conditional statement
• Introduction to User defined primitives (UDP’s)
• Combinational UDP’s
• Sequential UDP’s
• Level triggered UDP’s
• Edge triggered UDP’s
• Introduction to System Verilog
• Programming

  VHDL

• History
• Capabilities
• Overview
• Features of VHDL
• Language abstractions
• Concurrent VHDL
• Signal assignment
• Transport and inertial delays
• Concurrency
• Concurrent control statements
• Behavior and data flow modeling
• Data Types and synthesizable data type
• Advanced data types
• Subtypes
• Multi dimensional array
• Relational and arithmetic operators
• Vector assignment
• Bit string and literal
• Slice of array
• Sequential VHDL
• Concurrent and sequential data processing
• Processes
• Sequential Control statements
• Clocked sequential processes
• Synchronous and asynchronous process
• Postponed process
• Libraries
• Packages
• Subprograms
• Functions
• Procedures
• Structural VHDL
• Components declaration and specification
• Generic components
• Configurations
• State Machine
• Moore machine
• Mealy machine
• State machine with clocked output
• Different level of test benches
• Case study

CMOS

• Introduction of MOS device
• N- Mos
• P-Mos
• CMOS
• Structure of MOS cells and their transfer characteristics
• Device sizing
• Ratioed Logic
• Non ratioed logic
• CMOS as a switch
• Estimation of parasitic values
• Rise and fall times
• Power dissipation
• Design of complex circuit
• Fabrication steps

SYNTHESIS AND FPGA

• Introduction to PLD’S
• Introduction to PAL,
• Introduction to PLA
• Introduction to FPGA,
• FPGA architecture
• Different devices of XILINX series
• FPGA and logic synthesis
• Translation
• Area optimization
• Timing optimization
• Technology mapping
• Timing analysis
• Design format
• Reporting files
• FPGA implementation
       

ASIC

• Introduction of ASIC Design
• Flow Diagram
• Specifications
• Schematic cell Design.
• Design Rule Checks,
• Micron Rules
• Lambda rules of the design
• Fabrication methods of circuit elements
• Layout design of different cells
• Diff. Library cell designing, NAND, NOR, NOT, X-OR etc
• Circuit Extraction
• Electrical rule check
• LVS
• Post-layout Simulation
• Parasitic extraction
• Antenna effect
• Electro migration effect
• Body effect
• Inductive and capacitive cross talk
• Drain punch through, etc.
• Design format
• Timing analysis
• Backanotation
• Post layout simulation
• Spice modeling
• simulation technique
• Analysis of analog and digital circuits, circuit elements, operating point, AC and DC analysis.
• Transfer Characteristics, Transient responses, Noise analysis of current and voltage
 

Embedded System design Module

MODULE I: BASICS OF OS & PROGRAMMIMNG CONCEPTS

 OPERATING SYSTEM

• System Components/Services
• Introduction to Process Management
• Multiprogramming, threading, tasking and processing
• CPU Scheduling
• Basic concept
• Scheduling criteria
• Scheduling Algorithm
• Multi-Process Scheduling
• Real Time Scheduling System Components/Services
• Process Synchronization
• Semaphores
• Critical Region
• Monitors
• Deadlocks
• Deadlock Characterization
• Method for handling deadlocks
• Deadlock prevention
• Deadlock Avoidance
• Introduction to memory management
• Logical Address
• Physical Address
• Swapping
• Memory Management
• Contiguous Allocation
• Paging
• Segmentation
• Segmentation with paging
• Virtual Memory Pages (291-317)
• Demand Paging
• Page Replacement
• Page-Replacement Algorithm
• Thrashing
• File-System Interface Pages (337-360)
• Direct Memory Access Pages (406-420)
• Application I/O Interface
• Kernel I/O Subsystem
• Secondary –Storage Structure Pages (431-444)
• Disk Structure
• Disk Scheduling
• Disk Management
• Swap-Space Management
• Disk Reliability
• Network Structure
• Motivation
• Topology
• Network Type
• Distributed Operating System Pages
• Comparison of different operating system(window NT/Linux/Unix)

RTOS FUNDAMENTALS(RTLinux)

• Introduction to Real time systems and Real Time Operating Systems
• Real Time OS Concepts
• Installation of RTLinux /
• RTLinux Architecture, Module Concept, Linking a module with the kernel)
• Introduction to basic kernel API
• Real Time FIFO, Inter Process Communication between RT Task and Linux Process
• IPC using shared memory, Mail boxes, Hard & Soft Interrupts, Interrupt Handling in
• Configuring and Compiling RTLinux.
• Introduction to RTAI
• Comparison of various Real Time operating Systems

 Linux Shell Programming

• History
• Overview
• Additional Features of Linux
• Getting Acquainted with the Linux Environment
• The Linux File System
• The Shell
• Command Line
• Standard I/O
• Redirection
• Pipes
• Components of a GUI
• Vi Editor
• Features
• Command Mode
• Input mode
• Searching and Substituting for a String
• Misc. Commands
• Bourne Again Shell
• Simple Shell Script
• Job Control
• Directory Stack Manipulation
• Processes
• Parameters
• History
• Command Line Expansion
• Shell Programming Pages
• Control Structures
• Functions
• TC Shell
• Features
• Redirecting Standard Error
• Word Completion
• Variables
• Control Structures
• Advanced Shell Programming
• Programming Tools
• Background
• Make utility
• System Calls

SOFTWARE ENGINEERING CONCEPTS

• Introduction to SE
• The software process SDLC
• Describe and compare different SDLC models
• Project management
• Software implementation and maintenance
• Structured programming, language standards
• Software testing SQA, ISO, CMM Configuration management
• Software process and project metrics
• Design concepts

PROGRAMMING WITH C++ & DS

• Difference between C and C+
• Linux C++ Debugging
• Class and Objects
• Constructors and Destructors
• Inheritance
• Multiple Inheritances
• Friend functions and Classes
• Polymorphism
• Overloading functions
• Copy Constructors
• Run Time Polymorphism
• Virtual Functions
• Class and Function Templates
• Exception Handling
• Namespaces
• File Handling
• STL
• RTTI
• Advanced Typecasting
• Concurrency & Misc.
• Implement concurrency in C++.

Introduction to Data Structures

• Algorithms and Abstract data types, Complexity of Algorithms
• Linked lists – types, implementation and applications
• Stacks – Implementation and applications
• Queues – types, implementation and applications
• Various Searching and Sorting Algorithms
• Trees – types, implementation and applications
• Graphs – implementation and applications

 PROGRAMMING WITH LINUX INTERNALS

• File System Management – File concepts, Allocation and protection
• Mechanisms
• I/O and Secondary Storage Management
• Linux Architecture and System Call interface
• Processes & Signal API and POSIX thread API
• IPC Mechanisms (Pipes, FIFOs, Semaphores, Shared Memory)
• IPC Mechanisms (Message Queues and Sockets)
• Memory Management in Linux, Interrupts and Timers
• Introduction to kernel module programming

MODULE III: MICROCONTROLLER & DD

 8-BIT MICROCONTROLLERS AND INTERFACING

• Processor Architecture (Princeton and Harvard) RISC & CISC Microcontrollers Features & Memories
• Internal Architecture Addressing Modes Overview Instruction Set
• Data Movement Instructions Memory Instructions Arithmetic & Bit Operation Instructions
• Hardware Features Reset & System Clock /Oscillators Timers, Input Capture & Output Compare Modes
• Application Design Power, Oscillator & Reset Circuitry I/O Ports
• Interfacing LED’s, Switches & LCD Parallel Interface
• Interfacing Hardware to Microcontroller Types of ADC and DAC Example Interfacing of ADC & DAC to Microcontroller
• Serial Interface through RS232 I2C
• SPI Communication
• CAN Interface & USB Interfacing

 16/32 BIT ARM CONTROLLER

• Introduction to 16/32-bit Processors
• The ARM Architecture, Overview of ARM, Register Set and Modes
• ARM Processor Core ARM7TDMI & ARM 9TDMI, Data Path and Instruction Decoding
• ARM Instruction Set Introduction to Exceptions Conditional Execution, Branch, Branch Link and Branch Exchange
• ARM Development Environment Assembler and Compilers Linkers and Debuggers
• Software Interrupts Data Processing Instructions Multiple Register Transfer Instruction
• Thumb Instruction Set Mixing ARM & Thumb Instructions
• Architectural Support for High Level Language Data Types
• Floating Point Data Types Expressions, Conditional Statements and Loops
• Memory Hierarchy Memory Interfacing Memory Size & Speed Cache
• Architectural Support for Operating System ARM System Control Coprocessor CP15 Protection Unit Registers
• ARM MMU Architecture Synchronization Context Switching Enhanced DSP Extension

DEVICE DRIVER PROGRAMMING

• Introduction to Device Driver
• Kernel configuration (adding modules)
• Types of device drivers
• Building and running modules
• Building character drivers
• Debugging techniques
• Interrupt Handling
• Memory Handling
  

Project Work  :

 Project Work  : ( 4 WEEKS ) Embedded and VLSI application.

Submission of Application

Registration for the course would be done ONLINE. It is advised to read the General Instructions carefully before filling up the Application Form. Payment for registration can be done through DD or Credit Card mode. Registration fee is Rs. 300/- . If the mode is DD then a demand draft of Rs. 300/- in favour of CDAC, Noida payable at NOIDA has to be prepared. DD prepared should be before date of registration .  Any draft prepared after last of registration shall not be accepted. Candidates have to send a print out of the Application Form along-with self attested photocopies of mark sheets and DD (if applicable) so as to reach the venue on or before the last date of registration .

Course Commencement

In a year, twice as under:

1.    Tentatively 1st Monday of February

2.    Tentatively 1st Monday of August

Entrance Exam Venue

 CDAC, Noida